1. Field of the Invention
The invention relates to a test system for testing connectable integrated circuits in particular a method for configuring a test system.
2. Description of the Related Art
Semiconductor components are usually tested in parallel, that is to say that a plurality of components are connected to a test system in parallel via test channels and tested simultaneously with identical test patterns. The components to be tested in parallel are usually connected to a common current supply. If an excessively large current flows through one of the components on account of a defect, e.g. on account of an internal short circuit or the like, then this could lead to a voltage drop on the supply lines and the supply of the remaining functional components to be tested would no longer be ensured, and so the latter would be assessed as defective.
In order to avoid this, each component can be connected to its own voltage supply unit, a large number of supply units being required particularly in the case of test applications in which a very large number of integrated components are to be tested in parallel, e.g. during the wafer level burn-in. This approach is very complicated and causes very high costs.